Microcircuit devices and other integrated circuits (“ICs”) are used in a wide variety of products, such as automobiles, microwaves, personal computers, etc. Designing and fabricating such devices typically involves many steps, steps that have become known as a “design flow.” The particular steps of a design flow are highly dependent on various factors, such as the type of circuit to be designed, its complexity, the design team's preferences, and the microcircuit fabricator's or foundry's preferences or limitations.
Generally, large scale integrated circuits and other integrated devices typically are designed through a complex sequence of transformations that convert an original performance specification into a specific circuit structure. Automated software tools currently may be used for many of these design transformations. A common high level description of an integrated circuit may be provided in languages such as VHDL and VERILOG® (“VHDL” stands for “very high speed integrated circuit hardware description language;” “VERILOG®” is a registered trademark for Computer Programs for Computer-Aided Engineering Design for Electrical Engineering owned by Gateway Design Automation Corp. of Littleton, Mass.). One embodiment of VHDL is described in greater detail in “IEEE Standard VHDL Language Reference Manual,” ANSI Std. 1076-1993, published Jun. 6, 1994. One embodiment of VERILOG® is described in greater detail in “IEEE Standard 1364-1995.” These documents are entirely incorporated herein by reference. The description of the integrated circuit at this stage of a design often is called a “net list,” and it represents the specific electronic devices of the desired circuit (e.g., transistors, resistors, capacitors, their interconnections, etc.) that will achieve the desired logical result. Preliminary estimates of timing also may be made at this stage, assuming that each device in the desired integrated circuit will have a characteristic speed associated with it. The “netlist” may be considered as corresponding to the level of representation displayed in conventional circuit diagrams.
Once the relationships between the various circuit elements have been established, the design again is transformed, this time into the specific geometric elements that define the exact shapes that will be present to form the individual elements of the circuit. Automated tools exist to convert a “netlist” into a physical layout for the corresponding integrated circuit (e.g., custom layout editors, such as “IC Station” available from Mentor Graphics Corp., or “Virtuoso” available from Cadence Design Systems, Inc.). Automated place and route tools (conventional and commercially available) also can be used to define the physical layouts, especially for wires that will be used to interconnect logical elements of a design. FIG. 1 illustrates one example approach for converting a netlist to a corresponding physical layout. The “layout” defines the specific dimensions of the gates, isolation regions, interconnects, contacts, and other device elements that form the physical devices, and it usually represents these shapes with polygons defining their boundaries.
A layout typically contains data layers that correspond to the actual layers to be fabricated in the circuit (e.g., to be fabricated by a photolithographic process). Layouts also typically contain cells that define sets of particular devices within the circuit. Cells typically contain all the polygons on all the layers required for the fabrication of the devices it contains. Cells may be nested within other cells, often in very intricate arrangements. The structure of cells often is called a “data hierarchy.” Typical formats for data representing the polygons of a physical layout include GDS-II, CIF, OASIS, etc.
Once a layout is created, the layout may be verified to insure that the transformation from netlist to layout has been properly executed and that the final layout created adheres to certain geometric “design rules.” These two checks often are called an “LVS” (layout versus schematic) check and a “DRC” (design rule check), respectively. To perform this verification, several products have been created, including DRACULA™ (available from Cadence Design Systems, Inc. of San Jose, Calif.), HERCULES™ (available from Avant! Corporation of Fremont, Calif.), and CALIBRE® (available from Mentor Graphics Corporation of Wilsonville, Oreg.). When anomalies or errors are discovered, e.g., elements of a layout too close to one another, etc., the designer must then investigate the error and, if necessary, correct it before the layout is sent to a mask shop for mask manufacturing and wafer fabrication. Failure to correct such errors may result in production of masks that produce circuits having a high incidence of failure (e.g., a high percentage of short circuits, bridging problems, and the like).
An additional checking step also often is used for layout verification. FIG. 2 illustrates an additional approach to conversion of a netlist to a physical layout. This approach provides a simulation based software engine that predicts what manufacturing distortions will occur during lithographic patterning. If the magnitude of these errors is determined to be significant, corrections may be made using some form of “optical proximity correction” (“OPC”). OPC can correct for image distortions, optical proximity effects, photoresist kinetic effects, etch loading distortions, and other various process effects. Phase-shifting features also may be added to the layout at this point to enhance contrast, e.g., using a phase-shift mask (“PSM”). Examples of this type of checking and correction can be found, for example, in C. Spence, et al., “Automated Determination of CAD Layout Failures Through Focus: Experiment and Simulation,” Optical/Laser Microlithography VII, Proceedings of SPIE 2197 (1994), pp. 302-313, and E. Barouch, et al., “OPTIMASK: An OPC Algorithm for Chrome and Phase-Shift Mask Design,” Optical/Laser Microlithography VIII, Proceedings of SPIE 2440 (1995), pp. 192-206. These documents are entirely incorporated herein by reference. These techniques include operating on a layout with a series of distinct software tools that execute all the required steps in sequence.
FIG. 3 is a conceptual illustration of an example of processes for integrated circuit design verification and correction. In this illustrated example, each of the process steps is executed by a stand-alone software tool. The original IC layout 300 describes the physical circuit layers from which masks and/or reticles are created to realize the circuit described by a design layout. The original IC layout 300 may be, for example, a GDS-II description of the integrated circuit to be manufactured, or another layout format, like those mentioned above.
Data import process 310 converts the original IC layout 300 to a format for storage in verification database 315. The data, as stored in verification database 315, may be used by a layout versus schematic (“LVS”) tool 320 and a design rule checking (“DRC”) tool 325 to verify the design of original IC layout 300. Upon completion of LVS and DRC verification, the data stored in verification database 315 is exported by data export process 330.
This data then is imported by data import process 335, which converts the exported data to a format used for a phase shift mask (“PSM”) database 340. PSM tool 345 operates on the data stored in PSM database 340 to perform phase shifting where appropriate. Examples of stand alone PSM assignment tools are SEED (discussed in the Barouch article identified above) and the iN-Phase™ product now available from Synopsys, Inc. of Mountain View, Calif. The data describing the phase shifted layout(s) are exported from a PSM database 340 by data export process 350.
Data import process 355 imports the data generated by the PSM tool to an optical proximity correction (“OPC”) database 360. The OPC database 360 typically is a flat database, meaning that all the polygons of a layer of the circuit are contained within a single cell, with no hierarchical structure. Data import process 355 typically converts data from a hierarchical representation to a flat representation in the OPC database 360. OPC tool 365 performs OPC operations on the data stored in OPC database 360. Examples of stand alone OPC tools are OPTIMASK, discussed in the above-identified Barouch article, and Taurus™ available from Avant! Corporation of Fremont, Calif. Data export process 370 exports the data stored in OPC database 360.
The data generated by the OPC tool 365 then typically is imported into a simulation tool to confirm that the OPC will have the desired corrective effect. This action is sometimes called an “optical rule check,” or “ORC.” Once this check is complete, the data may be exported for use in an IC manufacturing process 395. If desired, as a final verification step, LVS tool 320 and/or DRC tool 325 also may be used on the output of OPC database 360. Performing another check with LVS tool 320 and/or DRC tool 325 requires another import and export by data import process 310 and data export process 330, respectively.
Further variations on the systems and methods described above are described in U.S. Pat. No. 6,425,113 to Anderson, et al., which patent is entirely incorporated herein by reference.
Complex “system-on-chip” (“SoC”) layouts in integrated circuit designs often are assembled using cells from many sources. Some of the layouts combined into a single SoC contain cells that have been designed with exceptions to the general design rules governing the overall integrated circuit (also called “golden cells” or “master cells” in this specification). For example, memory arrays and/or other memory-containing cells often will have physical layouts with spacings, dimensions, and other features that do not comport with the general constraints or general “design rules” placed on other portions of an IC design, yet these special cells are known to function correctly and are known to be capable of proper layout and manufacture. Typically, these cells will be identified as errors during conventional design rule checks, and these errors will have to be investigated and cleared by the designer and/or IC manufacturer before the mask, chip, or circuit is manufactured. Such investigation and clearance procedures are tedious and time-consuming, particularly when the layout contains many structures corresponding to a master cell.
In some systems and methods, these special cells may be identified and handled as “exceptions” during conventional design rule checking (as described above), and then separate design rule check runs may be required for these exceptional cells. Even in such systems and methods, the requirements for special handling and/or separate design rule checks can become tedious, overly complex, and very time-consuming, particularly when the number of exceptions and exceptional cells becomes large, as is common in many SoC designs.
It is not adequate to merely identify areas in an IC design as corresponding to a “master cell” and stopping the design rule check at that point. For various reasons, an IC designer may change one or more features associated with the “master cell” design in a specific layout (e.g., to enable it to interact with other portions of the IC) thereby changing the master cell design, which can invalidate its status as an approved exception to the conventional design rules. As another example, approved “master cell” designs may change over time, but some designers still may be using older versions of the master cell (e.g., by copying from old designs, by missing recent updates to the master cell design, etc.). These older versions may no longer be pre-approved for use in IC designs. In such instances, merely identifying a “master cell” in a layout may result in the introduction of unapproved and/or erroneous cell structures into an IC design layout. Layouts having such cells may be more prone to failures when finally embodied in a chip.
Accordingly, it would be useful in the art to provide systems and methods that: (a) will allow “in-line” identification and location of cells intended to correspond to previously designated master or golden cells, and/or (b) will allow in-line determination of whether the master cell, as used in the IC layout, actually corresponds to a current and previously approved master cell layout and structure.